Title :
Dual-loop digital PLL design for adaptive clock recovery
Author :
Kim, Tae Hun ; Kim, Beomsup
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggests an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period
Keywords :
digital phase locked loops; jitter; logic design; mobile communication; adaptive clock recovery; bandwidth adjusting algorithm; carrier recovery; clock recovery; digital data transmission receivers; disk drives; dual-loop digital PLL design; hardware requirement; jitter reduction; jitter variance; local area networks; mobile communications; noise environment; recursive least squares criterion; Bandwidth; Clocks; Data communication; Frequency; Hardware; Jitter; Noise reduction; Phase locked loops; Steady-state; Working environment noise;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669499