Title :
A parallel-amplification parallel-summation logarithmic amplifier for UHF RFID reader
Author :
Yong, Zhang ; Lei, Chen ; Xiao-jun, Zhang ; Zong-sheng, Lai
Author_Institution :
Dept. of Microelectron. & Solid-Stare Electron., East China Normal Univ., Shanghai, China
Abstract :
This paper describes a four gain paths parallel-amplification parallel-summation logarithmic amplifier (PPLA). It is used in the UHF RFID Reader as a part of the ASK demodulating system to compress the high dynamic range input signal. Compared with the successive detection logarithmic amplifier (SDLA), the PPLA has wider bandwidth, and is easier to meet requirement of the system stability. The presented PPLA is implemented in IBM 0.18 ¿m CMOS technology with dynamic range of 70 dB, bandwidth of 1 MHz, and power dissipation of 19 mW.
Keywords :
CMOS integrated circuits; UHF amplifiers; radiofrequency identification; radiofrequency integrated circuits; ASK demodulating system; IBM CMOS technology; UHF RFID reader; bandwidth 1 MHz; high dynamic range input signal; parallel-amplification parallel-summation logarithmic amplifier; power 19 mW; power dissipation; size 0.18 mum; Bandwidth; CMOS technology; Circuits; Dynamic range; Microelectronics; Performance gain; Radiofrequency identification; Stability; Topology; Voltage; PPLA; RFID; RSSI;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351373
