Title :
A low power self-sampling IF FSK receiver
Author :
Xu, Yang ; Chi, Baoyong ; Wang, ZhiHua
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A low power IF FSK receiver is presented. The receiver consists of one limiter and one self-sampling FSK demodulator. The limiter uses the replica biasing circuit technique to avoid the effects of PVT variation. To minimize the power consumption, a low supply VCDL is adopted, and the reference clock frequency of DLL is also decreased. The receiver has been implemented in 0.18 ¿m CMOS process and the simulated results show that the receiver could accurately demodulate the signal with a data rate of 2 Mbps and a IF carrier frequency of 10 MHz and achieves a IF carrier frequency offset tolerance of 1 MHz. The power consumption of the IF FSK receiver is 2.64 mW. The demodulator part consumes only 0.48 mW.
Keywords :
CMOS integrated circuits; delay lock loops; demodulators; frequency shift keying; low-power electronics; receivers; CMOS process; DLL; bit rate 2 Mbit/s; frequency 10 MHz; limiter; low power self-sampling IF FSK receiver; power 0.48 mW; power 2.64 mW; power consumption; reference clock frequency; replica biasing circuit technique; self-sampling FSK demodulator; size 0.18 mum; Circuits; Clocks; Delay lines; Demodulation; Dynamic range; Energy consumption; Frequency shift keying; Harmonic distortion; Voltage; Wireless sensor networks; CMOS integrated circuits; Low IF receiver; frequency shift keying (FSK) demodulator;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351377
