Title :
A sample/hold circuit for 80MSPS 14-bit A/D converter
Author :
Kunguang, Xiao ; Yuxing, Wang ; Minyuan, Xu ; Chan, Zhu
Author_Institution :
Sichuan Inst. of Solid-States, Chongqing, China
Abstract :
In this paper, a sample/hold circuit for switched capacitor structure in 0.35 ¿m CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80 MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3 V is -90 dB at 80 MSPS with input signal of 2 Vpp. As a result, the DNL is 0.8/-0.9 LSB, the INL is 3.1/-3.7 LSB, the SNR is 70.2 dB,and the SFDR is 89.3 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; capacitors; harmonic distortion; sample and hold circuits; 14-bit pipelined A/D converter; CMOS process technology; amplifier; channel injected charges; circuit simulation; differential unity gain structure; folded cascode gain intensified structure; maximum harmonic distortion; sample-hold circuit; sequential control; switched capacitor structure; voltage 2 V; voltage 3 V; Analog integrated circuits; Circuit noise; Laboratories; Operational amplifiers; Sampling methods; Signal processing; Signal sampling; Switched capacitor circuits; Switching circuits; Switching converters; 0.35um CMOS; A/D converter; SNR; linearity; sample/hold; switched capacitor circuit;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351390
