A sample/hold circuit for 80MSPS 14-bit A/D converter

In this paper, a sample/hold circuit for switched capacitor structure in 0.35 ¿m CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80 MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3 V is -90 dB at 80 MSPS with input signal of 2 V_pp. As a result, the DNL is 0.8/-0.9 LSB, the INL is 3.1/-3.7 LSB, the SNR is 70.2 dB,and the SFDR is 89.3 dB.