Title :
A 1.8V CMOS polar transmitter front-end for 900MHz EDGE system
Author :
Ren, Ran ; Yan, Taotao ; Jiang, Peichen ; Hu, Hao ; Zhou, Jianjun
Author_Institution :
CARFIC (Center for Analog/RF Integrated Circuits) Lab., Shanghai Jiao Tong Univ., Shanghai, China
Abstract :
A 900 MHz low-noise high-linearity polar transmitter front-end for EDGE system is presented, including a multiplier as well as a driver amplifier. The whole circuit is implemented in IBM 0.18 ¿m CMOS process. The multiplier and DA provide output power ranging from -30 dBm to 4.5 dBm, an ACPR of -63 dBc at 400 KHz offset and an output noise of -167 dBm/Hz at 20 MHz offset. The spurious around 2nd and 3rd harmonics are -46 dBc and -39 dBc respectively. The carrier suppression is -45dBc. The whole circuit consumes 23~56 mA from a 1.8 V supply voltage according to different gain levels.
Keywords :
3G mobile communication; CMOS integrated circuits; radio transmitters; radiofrequency integrated circuits; CMOS polar transmitter front-end; EDGE system; IBM CMOS process; carrier suppression; current 23 mA to 56 mA; frequency 900 MHz; low-noise high-linearity polar transmitter front-end; multiplier; size 0.18 mum; voltage 1.8 V; Amplitude modulation; Communication standards; Driver circuits; GSM; Linearity; Phase modulation; Radio access networks; Radio frequency; Transmitters; Wireless communication; EDGE system; driver amplifier; multiplier; polar transmitter;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351410
