A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery

A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for serial ATA with phase rotation is presented. The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3^rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the KVCO. Our spread spectrum clock generator (SSCG) for serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30~33 KHz. Spread-spectrum technique using PLL with a ¿¿ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512 fs and consumes 5.87 mW at 1.4 GHz. The EMI reduction is about 19.24 dB.