Title :
Fault tolerance performance of WSI systolic sorter
Author :
Horiguchi, Susumu
Author_Institution :
Dept. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
Presents a novel redundancy sorting array for WSI implementation. The redundancy sorting array consists of a mesh connected odd-even transposition sort and a modified bitonic sort with spare cells. The fault tolerance performance of the redundancy sorting array is discussed
Keywords :
VLSI; fault tolerant computing; integrated circuit technology; microprocessor chips; parallel architectures; sorting; WSI implementation; WSI systolic sorter; fault tolerance performance; mesh connected odd-even transposition sort; modified bitonic sort; redundancy sorting array; spare cells; Clocks; Concurrent computing; Fault tolerance; Fault tolerant systems; Information science; Production systems; Redundancy; Sorting; Systolic arrays; Very large scale integration;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63901
