Title :
Variation-aware study of BJT-based capacitorless DRAM cell scaling limit
Author :
Cho, Min Hee ; Kwon, Wookhyun ; Xu, Nuo ; Liu, Tsu-Jae King
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
Abstract :
The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.
Keywords :
CMOS integrated circuits; DRAM chips; bipolar transistors; electric field effects; 3D processing; BJT-based capacitorless DRAM Cell scaling limit; cell design; constant electric field methodology; device simulation; gate length; operating voltages; random sources; systematic sources; Electric fields; Logic gates; Random access memory; Resource description framework; Sensitivity; Sensors; Standards;
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
DOI :
10.1109/SNW.2012.6243319
