Title :
Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array
Author :
Seo, Joo Yun ; Kim, Yoon ; Park, Se Hwan ; Kim, Wandong ; Kim, Do-Bin ; Lee, Jong-Ho ; Shin, Hyungcheol ; Park, Byung-Gook
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Abstract :
In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).
Keywords :
flash memories; logic gates; technology CAD (electronics); 3D stacked NAND flash memory array; TCAD simulation; cell characteristics; double gate structures; gate dimensions; gate-all-around structures; high density storage capacity; program characteristics; stacked layers; variation effect; vertical etch profile; word line gate dimensions; Arrays; Educational institutions; Flash memory; Logic gates; Microprocessors; Solid modeling; 3D stacked NAND flash;
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
DOI :
10.1109/SNW.2012.6243320
