An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC

In the light of application to high-speed DAC, the design and achievement of a novel high-performance CMOS LVDS receiving circuits are described in this paper. By introduction of intrinsic offset, a fixed hysteresis voltage is obtained. The whole circuit doesn´t need any local feedback, and the high-speed performance of the original circuit doesn´t change with introduction of hysteresis voltage. Therefore the circuit has twofold advantages: a stable hysteresis voltage and a high-speed operation. The circuit was developed in chartered 0.35 μm CMOS process technology. The tested results showed that the circuit worked stably at an operational voltage of 3.3 V at a transmission speed of 2.4 Gb/s. The chip size of the circuit was 0.021 mm², and the power consumption of the circuit was 8 mW.