SYNTEST: a method for high-level SYNthesis with self-TESTability

Author

Papachristou, Christos ; Chiu, Scott ; Harmanani, Haidar

Author_Institution

Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

458

Lastpage

462

Abstract

The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs

Keywords

built-in self test; integrated circuit testing; logic testing; SYNTEST; allocation; behavioral description; constraint estimation; high-level SYNthesis; scheduling; self-testable RTL designs; structural design style; structural testability model; system-level synthesis tool set; testability tradeoffs; user-defined constraints; Automatic testing; Built-in self-test; Circuit testing; Costs; High level synthesis; Logic testing; Process design; Registers; Scheduling; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139947

Filename

139947