DocumentCode :
2652433
Title :
A single-event transient hardened phase-locked loop in 0.18 µm CMOS process
Author :
Zhenyu, Zhao ; Minxuan, Zhang ; Jihua, Chen ; Bin, Guo
Author_Institution :
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
284
Lastpage :
287
Abstract :
By implementing a novel complementary current limiter (CCL), a phase-locked loop (PLL) has been developed for improved single-event transient (SET) tolerance in 0.18 μm CMOS process. Simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 92.8%, and reduce the recovery time of the PLL by up to 76.4% in the presence of SETs in the charge pump (CP). And it can also improve the error pulses and phase displacement of the output clock greatly. Moreover, the CCL circuit can be readily applied to other PLL topologies.
Keywords :
CMOS integrated circuits; charge pump circuits; phase locked loops; voltage-controlled oscillators; CCL circuit; CMOS process; PLL topologies; charge pump; complementary current limiter; error pulses; phase displacement; single-event transient hardened phase-locked loop; size 0.18 μm; voltage perturbation; voltage-controlled oscillator; CMOS process; Charge pumps; Circuit simulation; Circuit topology; Clocks; Current limiters; Neutrons; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; RHBD; charge pump; phase-locked loop; single-event transient;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351458
Filename :
5351458
Link To Document :
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