A single-event transient hardened phase-locked loop in 0.18 µm CMOS process

By implementing a novel complementary current limiter (CCL), a phase-locked loop (PLL) has been developed for improved single-event transient (SET) tolerance in 0.18 μm CMOS process. Simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 92.8%, and reduce the recovery time of the PLL by up to 76.4% in the presence of SETs in the charge pump (CP). And it can also improve the error pulses and phase displacement of the output clock greatly. Moreover, the CCL circuit can be readily applied to other PLL topologies.