DocumentCode :
2652494
Title :
Statistical variability study of a 10nm gate length SOI FinFET device
Author :
Cheng, Binjie ; Brown, Andrew R. ; Wang, Xingsheng ; Asenov, Asen
Author_Institution :
Sch. of Eng., Univ. of Glasgow, Glasgow, UK
fYear :
2012
fDate :
10-11 June 2012
Firstpage :
1
Lastpage :
2
Abstract :
A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.
Keywords :
MOSFET; SRAM chips; elemental semiconductors; silicon-on-insulator; statistical analysis; FER-induced quantum confinement variation; FinFET technology; RDD induced S-D resistance variation; Si; comprehensive statistical variability simulation; device operation regions; gate length SOI FinFET device; on-current behaviour; size 10 nm; statistical SRAM cell simulation; statistical reliability simulation; subthreshold behaviour; trap fin configurations; Correlation; Degradation; Doping; Electrostatics; FinFETs; Logic gates; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
ISSN :
2161-4636
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
Type :
conf
DOI :
10.1109/SNW.2012.6243343
Filename :
6243343
Link To Document :
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