Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer

We proposed a novel CTF memory structure with surface patterned Si₃N₄ trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si₃N₄ trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10⁴ P/E cycles, was obtained.