Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer

Author

An, Ho-Myoung ; Kim, Kyong Heon ; Kim, Hee-Dong ; Cho, Won-Ju ; Kim, Tae Geun

Author_Institution

Sch. of Electr. Eng., Korea Univ., Seoul, South Korea

fYear

2012

fDate

10-11 June 2012

Firstpage

1

Lastpage

2

Abstract

We proposed a novel CTF memory structure with surface patterned Si₃N₄ trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si₃N₄ trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10⁴ P/E cycles, was obtained.

Keywords

flash memories; integrated circuit reliability; nanofabrication; nanopatterning; silicon compounds; CTF memory structure; Si₃N₄; charge-trap flash memory devices; data retention; memory windows; nanoscale surface patterns; program-erase cycles; reliability; surface memory-trap densities; surface patterned trap layers; ultrahigh density CTF devices; Capacitors; Charge carrier processes; Current density; Etching; Logic gates; Rough surfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop (SNW), 2012 IEEE

Conference_Location

Honolulu, HI

ISSN

2161-4636

Print_ISBN

978-1-4673-0996-7

Electronic_ISBN

2161-4636

Type

conf

DOI

10.1109/SNW.2012.6243350

Filename

6243350