Title :
Simulation of charge trapping memory with silicon nanocrystals embedded in silicon nitride layer
Author :
Peng, Yahua ; Liu, Xiaoyan ; Du, Gang ; Yang, Yan ; Kang, Jinfeng
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
A simulation method for evaluating the performance of CTM with incorporating nanocrystals into the charge trap layer is presented and the effects of bias voltage, charge trap distribution, nanocrystal size, temperature and gate dielectric layer´s thickness on program/erase/retention characteristic are studied. It can be a useful tool for designing nanocrystals based CTM.
Keywords :
CMOS integrated circuits; elemental semiconductors; nanostructured materials; semiconductor device models; semiconductor storage; silicon; silicon compounds; CTM performance; Si-Si3N4; Si-SiO2; bias voltage; charge trap distribution; charge trap layer; charge trapping memory simulation; gate dielectric layers thickness; nanocrystal size; program-erase-retention characteristic; silicon nanocrystals; Dielectrics; Logic gates; Nanocrystals; Performance evaluation; Temperature distribution; Tunneling;
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
DOI :
10.1109/SNW.2012.6243351
