DocumentCode
2652642
Title
Accessibility analysis on data flow graph: an approach to design for testability
Author
Chen, Chung-Hsing ; Wu, Chienwen ; Saab, Daniel G.
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
463
Lastpage
466
Abstract
Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nodes are accessible. A simple modification to the DFG that increases accessibility is presented
Keywords
VLSI; graph theory; integrated circuit testing; accessibility analysis algorithm; data flow graph; design for testability; internal circuit node; Algorithm design and analysis; Central Processing Unit; Circuit testing; Data analysis; Design for testability; Flow graphs; High level synthesis; Large-scale systems; Process design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139948
Filename
139948
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