Title :
3-D stacked NAND flash memory having lateral bit-line layers and vertical gate
Author :
Lee, Ju-Wan ; Jeong, Min-Kyu ; Park, Byung-Gook ; Shin, Hyungcheol ; Lee, Jong-Ho
Author_Institution :
Sch. of EECS & ISRC, Seoul Nat. Univ.Seoul, Seoul, South Korea
Abstract :
In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when CDE process was adopted after etching the BL stack.
Keywords :
NAND circuits; etching; flash memories; silicon; ΔVth terms; 3D stacked NAND flash memory structure; BL stack; CDE process; Si; etch damage removal; fabrication sequence; lateral bit-line layers; poly-Si BL layers; side surface; vertical gate; Etching; Fabrication; Flash memory; Ion implantation; Logic gates; Metals; Tunneling;
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
DOI :
10.1109/SNW.2012.6243354
