A method for testing partially programmable logic arrays in CPLDs

Author

Bailey, James ; Stroud, Charles ; Vocke, Nick ; Lau, Nancy ; Orso, William ; Tran, Camhong

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

2000

fDate

2000

Firstpage

175

Lastpage

180

Abstract

We describe a method for developing a minimal set of four test configurations with associated minimum sets of test patterns that completely tests reprogrammable Programmable Logic Arrays (PLAs) with partially programmable OR-planes typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck-at faults (including line and transistor faults) as well as all bridging faults without requiring hardware modifications in the PLA. Previous methods for testing reprogrammable PLAs have dealt only with fully programmable OR-planes

Keywords

automatic test pattern generation; integrated circuit testing; logic testing; programmable logic arrays; programmable logic devices; CPLDs; bridging faults; complex programmable logic devices; fault models; line faults; minimum sets; multiple stuck-at faults; partially programmable OR-planes; partially programmable logic arrays; reprogrammable PLAs; single stuck-at faults; test configurations; test patterns; transistor faults; Circuit faults; Circuit testing; EPROM; Fault detection; Hardware; Logic devices; Logic programming; Logic testing; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON Proceedings, 2000 IEEE

Conference_Location

Anaheim, CA

ISSN

1080-7725

Print_ISBN

0-7803-5868-6

Type

conf

DOI

10.1109/AUTEST.2000.885586

Filename

885586