A 14-bit successive-approximation AD converter with digital calibration algorithm

This paper implements a 14-bit successive approximation analog-to-digital converter (SAR ADC) design. The architecture and performance of the designed ADC is described. A digital calibration algorithm applied in this ADC has been emphasized in this paper. The correction codes of the calibrated capacitor are generated from the low bit to the high bit in the correction code generation state and are loaded in the calibration state. The digital control logic switches the capacitor array with the related correction code. The testing result indicates that the SAR ADC achieves a resolution of 14-bit at 200KSPS sampling rate.