A bidirectional overflow digital correction algorithm with a single bit redundancy used in the pipeline A/D converters

Author

Li, Ting ; Wang, Yuxin ; Li, Ruzhang ; Li, Kaicheng

Author_Institution

Nat. Lab. of Analog Integrated Circuits, Chongqing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

238

Lastpage

241

Abstract

A bidirectional overflow digital correction algorithm with a single bit redundancy used in the pipeline A/D converters is presented in this paper. The upper redundance codes and the lower redundance codes are introduced in this digital correction algorithm to correct the comparator offset so that the underflow and overflow of the input signal can be identified by the corrected output. The digital correction algorithm is used in a 16-bit 40 MS/s A/D converter in 0.35 Â¿m CMOS process. The tested results showed that the DNL is +0.76/-0.67 LSB and that INL is +2.7/-2.1 LSB without trimming.

Keywords

CMOS integrated circuits; analogue-digital conversion; codes; comparators (circuits); redundancy; CMOS process; bidirectional overflow; comparator offset; digital correction algorithm; pipeline A/D converters; redundance codes; single bit redundancy; size 0.35 mum; word length 16 bit; Algorithm design and analysis; CMOS process; Delay; Flowcharts; Pipelines; Quantization; Signal processing; Signal resolution; Testing; Voltage; A/D converter; bidirectional overflow; digital correction;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351482

Filename

5351482