Notice of Violation of IEEE Publication PrinciplesNew architecture of low voltage sigma-delta ADC

Notice of Violation of IEEE Publication Principles

"New Architecture of Low Voltage Sigma-Delta ADC"
by Jiaxin Ju, Wanrong Zhang, Haolin Du, Yanfeng Jiang, Yamin Zhang
in the Proceedings of the IEEE 8th International Conference on ASIC (ASICON), October 2009

After careful and considered review of the content and authorship of this paper by a duly
constituted expert committee, this paper has been found to be in violation of IEEE\´s
Publication Principles.

This paper contains significant portions of original text from the paper cited below. The
original text was copied with insufficient attribution (including appropriate references to
the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past
references to this paper, and future references should be made to the following article:

"A Low Voltage Sigma-delta ADC New Architecture"
by Liu Airong and Yang Huazhong
in Research and Progress of SSE Solid State Electronics, March 2009

A low voltage low power sigma delta modulator was presented. A sigma delta modulator architecture which was very adapt to low voltage low power applications was proposed. With the advantage of both unity gain sigma delta modulator and traditional sigma delta modulator, it relaxed the requirement of the OTA performance and decreased the complex of the circuit. For lower power consumption as soon as possible, the technique of negative resistance load was used to improve the dc gain of the current mirror OTA and the technique of Class-AB output stage was used for lower power consumption. Simulation results showed that with 0.18 um CMOS technology, 20 KHz signal bandwidth and oversampling rate of 156, the modulator achieved 93 dB dynamic range, the power consumption was 500 uW under 1 V supply voltage and the chip core size was 0.5 mm². Measure results showed t- at with 2 MHz sampling frequency and 1 KHz input signal the sigma delta modulator achieved 65 dB SNR and 60 dB SNDR.