A single channel 2GS/s 6-bit ADC with cascade resistive averaging

A single channel 2 GS/s 6-bit ADC with cascade resistive averaging is demonstrated in 0.18 ¿m CMOS. The proposed power efficient crossing connection method of averaging resistors has less reference voltage consumed than convention with excellent offset averaging. The peak DNL and INL are measured as 0.26 LSB and 0.21 LSB, respectively. The SNDR and SFDR have achieved 34.2 and 37.5 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The SNDR and SFDR maintain above 30 and 35 dB, respectively, up to 1000 MHz input signal and 900 MS/s. The proposed ADC, including onchip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.