The gate-bias influence for ESD characteristic of NMOS

Author

Liu, Juan ; Fan, Hang ; Li, Jianguo ; Jiang, Lingli ; Zhang, Bo

Author_Institution

State Key Lab. of Electron. Thin & Integrated Device, Univ. of Electron. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1047

Lastpage

1050

Abstract

The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46 V to 7.8 V with the negative gate bias changed from 0 V to -10 V, and reduced from 10.46 V to 5.92 V with the positive gate bias changed from 0 V to 3 V. Under appropriate gate bias, the ESD protection devices can obtain lower Vt1 and higher Vt2. It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.

Keywords

CMOS integrated circuits; electrostatic discharge; technology CAD (electronics); ESD characteristic; ISE TCAD; NMOS devices; gate bias influence; negative gate bias effect; CMOS integrated circuits; CMOS technology; Electronic ballasts; Electrostatic discharge; Low voltage; MOS devices; Protection; Resistors; Robustness; Variable structure systems; ESD; NMOS; TCAD; gate-bias effect;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351505

Filename

5351505