Title :
Register-constrained address computation in DSP programs
Author :
Basu, Anupam ; Leupers, Rainer ; Marwedel, Peter
Author_Institution :
Dept. of Comput. Sci., Dortmund Univ., Germany
Abstract :
This paper describes a new code optimization technique for digital signal processors (DSPs). One important characteristic of DSP algorithms are iterative accesses to data array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). We present a heuristic technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for array address computations in a program loop
Keywords :
optimising compilers; signal processing; storage allocation; DSP algorithms; DSP programs; code optimization technique; dedicated address generation units; digital signal processors; heuristic technique; iterative accesses; program loop; register-constrained address computation; Computer aided instruction; Computer science; Digital signal processing; Digital signal processors; Embedded computing; Instruction sets; Iterative algorithms; Program processors; Registers; Signal processing algorithms;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655974
