Low cost Design-for-Testability features for System-on-Chip: Case study

With the development of process technologies and increased complexity of chips, System-on-Chip (SoC) testing becomes more and more difficult. In this paper, low cost Design-for-Testability (DFT) features are presented for an industrial control application SoC, including at-speed test clock generation and test pattern compression. The proposed on chip at-speed test clock generation circuit is consisted of CLK GEN, CLK CHAIN, and CLK CONTROL. This circuit can be flexible enough to provide various at-speed clock pulses to detect timing-related defects. Our experimental results demonstrate that the proposed test scheme can gain high fault coverage and test compression ratio, which are 97.39% and 30%, satisfying the project demands.