DocumentCode :
2653625
Title :
Complexity and performance of computational arrays
Author :
Nadhamuni, Srikanth ; Aravena, Jorge L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
fYear :
1988
fDate :
0-0 1988
Firstpage :
360
Lastpage :
363
Abstract :
The authors use a case study to analyze the tradeoffs between speed and complexity in systolic array operation. First, a theoretical lower bound for performance is established. The use of currently available systolic arrays is considered. These arrays feature advanced characteristics such as nonplanar interconnections and multimode processing elements The arrays are provided with additional features to increase computational speed. The best performance obtained is still inferior to the theoretical optimum. To complement the study, the requirements of an architecture to achieve optimal performance are established.<>
Keywords :
cellular arrays; computational arrays; multimode processing elements; nonplanar interconnections; systolic array operation; Computer architecture; Computer displays; Concurrent computing; Fabrication; Iterative algorithms; Matrix decomposition; Switches; Systolic arrays; Transmission line matrix methods; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 1988., Proceedings of the Twentieth Southeastern Symposium on
Conference_Location :
Charlotte, NC, USA
ISSN :
0094-2898
Print_ISBN :
0-8186-0847-1
Type :
conf
DOI :
10.1109/SSST.1988.17074
Filename :
17074
Link To Document :
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