Title :
A new design of double edge triggered flip-flops
Author :
Pedram, Massoud ; Wu, Qing ; Wu, Xunwei
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing CMOS DET flip-flops. By simulating and comparing the proposed DET flip-flop with the traditional single-edge-triggered (SET) flip-flop, it is shown that the proposed DET flip-flop reduces power dissipation by half while keeping the same date rate
Keywords :
CMOS integrated circuits; SPICE; delays; flip-flops; logic design; CMOS DET flip-flop; CMOS DET flip-flops; SPICE; delay time; double edge triggered flip-flops; input signal; logic construction; logic functionality; power dissipation; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Delay effects; Flip-flops; Logic design; SPICE; Signal analysis;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669513
