An multi-rate LDPC decoder based on ASIP for DMB-TH

Author

Zhang, Xiaojun ; Tian, Yinghong ; Cui, Jianming ; Xu, Yuyin ; Lai, Zongsheng

Author_Institution

IMCS, East China Normal Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

995

Lastpage

998

Abstract

Based on ASIP (application specific instruction set processor), this paper propose a decoder architecture for LDPC (low density parity check codes) in the DMB-TH standard. The decoder use a five-stage pipeline, 32-bit RISC processor and it can supports three different code rates (0.4, 0.6 and 0.8) by only modifying the program. Based on XC4VLX150, at the max frequency of 126 MHz, the max throughput of the decoder can achieve 96 Mps for 10 TDMP-decoding Iterations. Compared with other GPP and DSP implementations, this ASIP simplify the control logical and enhance the flexibility.

Keywords

application specific integrated circuits; decoding; digital television; microprocessor chips; multimedia communication; parity check codes; reduced instruction set computing; ASIP; DMB-TH; RISC processor; TDMP; application specific instruction set processor; digital multimedia broadcasting; digital television terrestrial broadcasting; frequency 126 MHz; low density parity check code; multirate LDPC decoder; word length 32 bit; Application specific integrated circuits; Application specific processors; Block codes; Computer architecture; Digital signal processing; Instruction sets; Iterative decoding; Parity check codes; Reduced instruction set computing; Throughput; ASIP; DMB-TH; TDMP; decoder; multi-rate;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351527

Filename

5351527