Title :
Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units
Author_Institution :
Dept. of Electron., Politecnico di Milano, Italy
Abstract :
Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation
Keywords :
VLSI; error detection; fault tolerant computing; integrated circuit technology; microprocessor chips; parallel architectures; Berger codes; concurrent error detection; fault-localisation; fault-tolerant WSI array processors; parallel arithmetic-logic units; parallel computing units; unidirectional errors; Arithmetic; Computer architecture; Concurrent computing; Costs; Fault detection; Fault tolerance; Logic arrays; Logic design; Protection; Very large scale integration;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63902
