Architectural integration of RSA accelerator into MIPS processor

In the domain of information security, people are now prone to implement the cryptographic algorithm through hardware. Usually, these algorithms are designed as coprocessors and a system integrator must use some kind of protocol to correctly use it. This paper presents a convenient way to integrate RSA-engine onto MIPS processor based system by making use of the CP2 extension of MIPS architecture. A concrete implementation of RSA is given, and a dedicated hardware architecture is presented to integrate the MIPS processor and RSA accelerator. Also, software issues are raised and sample codes are given.