DocumentCode
2654002
Title
Space- and time-efficient BDD construction via working set control
Author
Yang, Bwolen ; Chen, Yirng-An ; Bryant, Randal E. ; O´Hallaron, D.R.
Author_Institution
Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1998
fDate
10-13 Feb 1998
Firstpage
423
Lastpage
432
Abstract
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of protocol and circuit designs increases. This paper addresses this issue by introducing three techniques based on working set control. First, we introduce a novel BDD construction algorithm based on partial breadth-first expansion. This approach has the good memory locality of the breadth-first BDD construction while maintaining the low memory overhead of the depth-first approach. Second, we describe how memory management on a per-variable basis can improve spatial locality of BDD construction at all levels, including expansion, reduction, and rehashing. Finally, we introduce a memory compacting garbage collection algorithm to remove unreachable BDD nodes and minimize memory fragmentation. Experimental results show that when the applications fit in physical memory, our approach has speedups of up to 1.6 in comparison to both depth-first (CUDD) and breadth-first (GAL) packages. When the applications do not fit into physical memory, our approach outperforms both CUDD and CAL by up to an order of magnitude. Furthermore, the good memory locality and low memory overhead of this approach has enabled us to be the first to have successfully constructed the entire C6288 multiplication circuit from the ISCAS85 benchmark set using only conventional BDD representations
Keywords
circuit CAD; computational complexity; formal verification; storage management; ISCAS85 benchmark set; binary decision diagrams; circuit designs; complexity; formal verification; memory compacting garbage collection algorithm; memory locality; memory management; partial breadth-first expansion; protocol; spatial locality; working set control; Binary decision diagrams; Boolean functions; Circuit synthesis; Computer science; Data structures; Formal verification; Government; Memory management; Packaging; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669515
Filename
669515
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