DocumentCode :
2654108
Title :
CMOL cell assignment based on dynamic interchange
Author :
Chu, Zhufei ; Xia, Yinshui ; Wang, Lunyao ; Hu, Meiqun
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
921
Lastpage :
924
Abstract :
A new method based on dynamic interchange for cell assignment task of CMOL, a hybrid integrated circuit architecture, is proposed. In this paper, we first transform AND/OR/NOT gates composed of logic circuits into NOT gates and two inputs NOR gates, and then map the NOR/NOT gates to CMOL cells. During mapping process, we first allocate adequate CMOL cell resources and then randomly map the gates to the CMOL cells, which can satisfy the architecture demand and require no overlap between cells. Then we adjust the gates by interchanging and inserting buffers for long distance gate pair. Experiment results on MCNC benchmark show that the proposed approach can result in faster running time than prior approaches.
Keywords :
CMOS integrated circuits; hybrid integrated circuits; logic circuits; logic gates; nanowires; AND gates; CMOL cell assignment; Cmosnanowiremolecular hybrid; MCNC benchmark; NOR gates; NOT gates; dynamic interchange; hybrid integrated circuit architecture; logic circuits; Algorithm design and analysis; Circuits and systems; Costs; Fabrication; Field programmable gate arrays; Hybrid integrated circuits; Latches; Logic circuits; Moore´s Law; Tiles; Algorithm; CMOL; Cell; Mapping; Placement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351545
Filename :
5351545
Link To Document :
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