DocumentCode
2654119
Title
A weighted statistical analysis of DPA attack on an ASIC AES implementation
Author
Qian, Guoyu ; Zhou, Ying ; Xing, Yueying ; Fan, Yibo ; Tsunoo, Yukiyasu ; Goto, Satoshi
Author_Institution
IPS, Waseda Univ., Kitakyushu, Japan
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
906
Lastpage
909
Abstract
Research on Differential Power Analysis (DPA) is becoming more and more popular nowadays. Against different hardware, DPA attack will lead to different results, e.g. attack on FPGA is easy but on ASIC is relatively difficult. However, how could we draw the conclusion that we finish a successful attack? How to build the connection between result data and successful rate is a meaningful topic. Same data with different statistical processing method will lead to different results. In this paper, we focus on DPA attack against an ASIC implementation. We analyzed two current statistical methods, pointed out the limitations. Then, we proposed a weighted statistical analysis method. According to number of traces and repetitions, we adjust the weight value. Finally, we improved the accuracy and efficiency of DPA attack on ASIC by reducing the number of traces used in attack.
Keywords
application specific integrated circuits; cryptography; field programmable gate arrays; integrated circuit testing; statistical analysis; ASIC; DPA; FPGA; advanced encryption standard; differential power analysis; weighted statistical analysis; Algorithm design and analysis; Application specific integrated circuits; Cryptography; Energy consumption; Field programmable gate arrays; Hardware; NIST; National electric code; Power measurement; Statistical analysis; AES; ASIC; Differential Power Analysis; Repetition Number Weight; Trace Number Weight;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351546
Filename
5351546
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