A 1Gsample/Sec non-recursive sharpened cascaded integrator-comb filter with 70 dB alias rejection and 0.003 dB droop in 0.18-µm CMOS

A new architecture for the implementation of very high speed digital decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter´s passband response. A SPT-encoded non-recursive technique is further applied to realize parallel computation and improve the maximum clock rate of the filter. With a 0.18-¿m CMOS process, the filter can achieve a greater than 1 GHz clock rate even as we trade off speed for power consumption and area. The maximum achievable clock rate exceeds 2.5 GHz in 0.18-¿m CMOS. Such high speed capability enables it to be employed in wide-band communication systems such as 3G cellular applications.