Title :
Design of low-power Complementary Pass-Transistor and ternary adder based on multi-valued switch-signal theory
Author :
Zeng, Xiaopang ; Wang, Pengjun
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
Abstract :
Based on study of previous full adders, this paper proposed a novel ternary full adder (TFA), which are implemented by using switch-level design technology in CPL (complementary pass-transistor logic) structure. Compared with traditional TFA: the circuit structure is simplicity and regulation in symmetry structure; The circuit delay is balanced and the circuit speed is increased and the circuit area is reduced by using switch-level design technology. A new TRCA (ternary ripple carry adder) is designed based on these TFA. The PSPICE simulation results indicate: the novel scheme has correct logic function and the character of clearly low power. It is suitable for high performance and low-power VLSI design.
Keywords :
SPICE; VLSI; adders; delay circuits; low-power electronics; PSPICE simulation; VLSI design; circuit delay; complementary pass transistor logic; logic function; low power electronics; multivalued switch-signal theory; switch-level design technology; ternary full adder; ternary ripple carry adder; Adders; CMOS logic circuits; Inverters; Logic circuits; Logic design; MOSFETs; Multivalued logic; Propagation losses; Signal design; Signal restoration; CPL; Low-power; Multiple-value logic; adder; switch-signal theory;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351560
