A Look-Up-Table Based Differential Logic to counteract DPA attacks

Dual-rail precharge (DRP) logic styles, such as wave dynamic differential logic (WDDL), have been proposed as a countermeasure against differential power analysis (DPA) for years. Because of the constant transition rate, the correlation between power consumption and signal values is significantly reduced. However, leakage still occurs in these logic styles caused by the difference of signal delay time. In this paper, a novel look-up-table (LUT) based differential logic (LBDL) is presented. The transition time of LBDL gates are independent of input values, hence the power consumption of LBDL is constant though the signals have different delays. Experimental results indicate that LBDL eliminates most of the leakage, while the performance and area costs are similar to WDDL.