Scalable and unified hardware architecture for montgomery inversion computation in GF(p) and GF(2n)

Computing the inverse of a number in finite fields GF(p) or GF(2ⁿ) is equally important for cryptographic applications. In this paper four optimized Montgomery inverse algorithms are proposed to achieve high speed and flexibility. Then a novel scalable and unified architecture for Montgomery inverse hardware that operates in both GF(p) and GF(2ⁿ) is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed, and it takes less number of clock cycle as the datapath of scalable design is large and can also achieve high clock frequency. Finally this work has been verified by modeling it in Verilog-HDL, implementing it under 0.18 ¿m SMIC technology. The result indicates that our work has advanced performance than other works.