DocumentCode
2654525
Title
A comparing study of technology mapping for FPGA
Author
Martin, Hans-Georg ; Rosenstiel, Wolfgang
Author_Institution
Dept. of Comput. Eng., Tubingen Univ., Germany
fYear
1998
fDate
23-26 Feb 1998
Firstpage
939
Lastpage
940
Abstract
This paper investigates some design flows to obtain final designs on Xilinx XC4000 FPGAs. The examples generated by high level synthesis were mapped including placement and routing. This reveals that the common criteria of area optimal or delay-optimal circuits should be enlarged by routability and computing time
Keywords
circuit layout CAD; circuit optimisation; field programmable gate arrays; high level synthesis; integrated circuit layout; network routing; FPGA design; Xilinx XC4000; area optimal circuits; delay-optimal circuits; design flows; high level synthesis; placement; routing; technology mapping; Adders; Cascading style sheets; Circuits; Delay effects; Design optimization; Field programmable gate arrays; High level synthesis; Logic; Network synthesis; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655979
Filename
655979
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