Title :
Power-aware FPGA packing algorithm
Author :
Yang, M. ; Xu, Hongying ; Almaini, A.E.A.
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
Field-programmable gate array (FPGA) packing is one of abstraction levels in the FPGA CAD design flow which is aimed to pack logic components into clusters. As a result, the cluster-based FPGA can significantly improve timing, routability and power consumption as well. This paper proposes a novel packing algorithm using priori wire length estimation before actual routing taken apart. In addition, global placement was taken apart before packing to have additional placement information, which is also guided for the algorithm to selectively pack closely related module into one cluster. Experimental results show that power-aware packing algorithm achieves 5% power reduction on average compared to traditional algorithm.
Keywords :
electronic design automation; field programmable gate arrays; integrated circuit design; integrated circuit metallisation; CAD design flow; FPGA packing algorithm; field programmable gate array packing; logic component; power aware packing algorithm; priori wire length estimation; Circuit simulation; Clustering algorithms; Computational modeling; Design automation; Energy consumption; Field programmable gate arrays; Logic; Power dissipation; Routing; Switches; Algorithm; EDA; FPGA; Power dissipation;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351571
