VLSI designs for high-speed Huffman decoder

Many video compression systems require a high-speed implementation of the huffman decoder. The recursive iteration of the decoding process limits the achievable decoding throughput with a given IC technology. Two classes of VLSI architectures for high speed implementation are designed: the tree-based architectures and the programmable logic array (PLA)-based architectures. A variable-length-code based on a popular video compression system is constructed and the pros and cons of each architecture are compared. The major parts of a pipelined constant-input-rate PLA-based architecture using a high-level synthesis approach are simulated. It is claimed that the decoding throughput of 200 Mb/s is achievable with CMOS 2.0 μm technology