• DocumentCode
    2654757
  • Title

    Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for Super Hi-Vision application

  • Author

    Huang, Yiqing ; Ikenaga, Takeshi

  • Author_Institution
    Inf. Production & Syst., Waseda Univ., Kitakyushu, Japan
  • fYear
    2009
  • fDate
    20-23 Oct. 2009
  • Firstpage
    183
  • Lastpage
    186
  • Abstract
    One super hi-vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217 MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC 0.18 um in worst work conditions (1.62 V, 125°C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5 k gates hardware.
  • Keywords
    edge detection; logic design; motion estimation; video coding; 16-pel scale processing; H.264/AVC; MB-split assignment; edge detection; fractional motion estimation; mode reduction; parallel enhanced low design; size 0.18 mum; subsampling technique; sum-of-absolute-transformed-difference; super hi-vision application; temperature 125 C; voltage 1.62 V; Automatic voltage control; Costs; Engines; Filtering; Filters; Hardware; Image edge detection; Motion estimation; Throughput; Video compression; FME; H.264/AVC; Super Hi-Vision;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2009. ASICON '09. IEEE 8th International Conference on
  • Conference_Location
    Changsha, Hunan
  • Print_ISBN
    978-1-4244-3868-6
  • Electronic_ISBN
    978-1-4244-3870-9
  • Type

    conf

  • DOI
    10.1109/ASICON.2009.5351576
  • Filename
    5351576