DocumentCode
2654951
Title
The research and design of parallel instruction targeted at substitution box
Author
Dai, Zibin ; Li, Wei ; Meng, Tao ; Chen, Tao
Author_Institution
Zhengzhou Inst. of Inf. Technol., Zhengzhou, China
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
155
Lastpage
158
Abstract
Based on the analysis of 41 popular block ciphers, we research the characteristics of conventional substitution boxes, and then analyze the realization methods of the substitution box. A efficient and flexible specific instruction is proposed, which can execute four kinds S-boxes substitution including 4-4, 6-4, 8-8, 8-32, and perform operation on different pages. Besides, it can meet the various demands of different rounds in encryption or decryption, and can execute eight groups 4-4 substitution operations in parallel, or four groups 8-8, or eight groups 6-4, or one group 8-32 in parallel. Furthermore, we extend the usage of special instruction to the VLIW structure, and then design the hardware module of the substitution box. Finally, the hardware module is fabricated on 0.18 ¿m CMOS process. Compared with other instruction design, it can flexibly and effectively realize the operation of substitution box.
Keywords
CMOS integrated circuits; cryptography; instruction sets; CMOS process; S-boxes substitution; VLIW structure; block ciphers; decryption; encryption; instruction design; size 0.18 mum; Algorithm design and analysis; Application specific processors; CMOS process; Cryptography; Frequency; Hardware; Information technology; Logic; Security; VLIW; Block ciphers; Instruction; Look up table; Substitution box; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351585
Filename
5351585
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