DocumentCode :
2654981
Title :
VLSI architecture of a low complexity face detection algorithm for real-time video encoding
Author :
Zhang, Tianruo ; Wang, Minghui ; Liu, Chen ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka, Japan
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
147
Lastpage :
150
Abstract :
Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detection for videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H.264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSI architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in CIF sequences.
Keywords :
VLSI; face recognition; video coding; videotelephony; H.264 encoder; VLSI architecture; content analyzer; content aware algorithm; estimation-and-verification process; low complexity face detection algorithm; power 1.45 mW; real time video encoding; video encoder; videophone face detection; Algorithm design and analysis; Bit rate; Computer architecture; Detectors; Encoding; Face detection; Hardware; Image coding; Pipelines; Very large scale integration; Face Detection; VLSI Architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351587
Filename :
5351587
Link To Document :
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