A LUT-based VRC model for random logic function evolution

Author

Bu, Haixiang ; Chen, Liguang ; Lai, Jinmei

Author_Institution

Microelectron. Dept., Fudan Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1

Lastpage

5

Abstract

Recently, the VRC (virtual reconfigurable circuit) has become a mainstream solution for EHW (evolvable hardware) research. In this paper, A LUT-based VRC model is proposed, which can be applied for random logic function evolution. Different kinds of LUTs with appropriate interconnections were studied on a FPGA-based platform. Research were also performed in this platform to compare with the current VRC model such as VRC1 [SinMan] and VRC2 [Sekan-ina]. The results show that 3-input LUT with a direct interconnection achieves about 8% improvement in fitness value after 20,000 generations, and obtains obvious progress in logic resource utilization rate.

Keywords

field programmable gate arrays; integrated circuit interconnections; logic design; table lookup; FPGA based platform; LUT based VRC model; Sekan-ina; SinMan; evolvable hardware; integrated circuit interconnections; logic resource utilization rate; random logic function evolution; virtual reconfigurable circuit; Field programmable gate arrays; Genetic algorithms; Hardware; Integrated circuit interconnections; Logic devices; Logic functions; Microelectronics; Programmable logic arrays; Resource management; Table lookup; EHW; Genetic Algorithm; LUT-based VRC; VRC;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351592

Filename

5351592