Title :
An energy-aware heuristic constructive mapping algorithm for Network on Chip
Author :
Chen, Yancang ; Xie, Lunguo ; Li, Jinwen
Author_Institution :
Nat. Univ. of Defense Technol., Changsha, China
Abstract :
Network on chip (NoC) is a promising interconnection solution for the ever-increasing systems complexity and design productivity gap. Mapping the IP cores onto a given platform is an important phase of NoC design which can greatly affect the performance and energy consumption of the chip. In this paper, we analyze the preexistent mapping algorithms, and categorize them into three classes according to the tracks of obtaining the near-optimal mapping. We present a fast hybrid heuristic constructive algorithm, i.e. CMAP, to map cores onto NoC architectures with the goal of minimizing the total communication energy consumption. The algorithm is applied to two real applications and a series of task graphs generated by TGFF package. The accuracy, efficiency and scalability of the proposed algorithm are confirmed by comparing the results of our algorithm with other mapping algorithms.
Keywords :
integrated circuit design; logic design; network-on-chip; CMAP algorithm; IP cores mapping; NoC architecture; NoC design; design productivity gap; energy consumption; energy-aware heuristic constructive mapping; near-optimal mapping; network on chip; systems complexity; Algorithm design and analysis; Energy consumption; Heuristic algorithms; Iterative algorithms; Network-on-a-chip; Neural networks; Packaging; Productivity; Scalability; System-on-a-chip; Constructive Mapping Algorithm; Edge Mapping; Network on Chip; Scalability;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351596