DocumentCode
2655241
Title
Transaction level model of NoC based on SystemC
Author
Wang, Jian ; Wang, Hong ; Yang, Zhijia
Author_Institution
Key Lab. of Commun. & Control, Chinese Acad. of Sci., Shenyang, China
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
97
Lastpage
100
Abstract
This paper presents a transaction-level on-chip communication network model, including routers and links, which can be easily employed in a system-level system-on-chip simulation framework for early functional verification and architecture analysis. The model is capable of providing NoC´s latency and throughput information during simulating process and developed in SystemC to achieve high simulation speed.
Keywords
network-on-chip; NoC; SystemC; functional architecture analysis; functional verification analysis; network on chip; routers; simulation process; system-level system-on-chip simulation framework; throughput information; transaction level model; transaction-level on-chip communication network model; Analytical models; Automatic control; Communication system control; Control systems; Delay; Laboratories; Natural languages; Network-on-a-chip; System-on-a-chip; Throughput; SystemC; network on chip; transaction-level model;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351599
Filename
5351599
Link To Document