A systolic circuit for fast Hartley transform

The authors present a systolic circuit for computing a fast algorithm performing the discrete Hartley transform (DHT). The proposed architecture employs a systolic elevator concept and CORDIC processors. The elevator assures local communications in the proposed algorithm, and the CORDIC processor makes it possible to enhance processing speed and exploit parallelism. The architecture appears to be regular and, therefore, very attractive for VLSI realizations. The computational cost necessary for computing the DFT (discrete Fourier transform) is also discussed with respect to other architectures.<>