An efficient parallel instruction execution method for VLIW DSP

Author

Sun, Mengjun ; Shen, Zheng ; He, Hu

Author_Institution

Dept. of Microelectron., Peking Univ., Beijing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

75

Lastpage

78

Abstract

LILY is a high performance VLIW DSP processor for multimedia applications, developed by Tsinghua University. The processor classifies the instructions, and determines whether the instructions should be issued in parallel according to the order of the instructions. Under this parallelism, LILY processor is capable of saving one bit of operation code in the condition of inserting very few no operation (NOP) instructions. In addition, it is needed to design a corresponding assembler to accommodate the above new parallelism, which aids LILY to complete the highly efficient method. The evaluation results show satisfactory suitability of the processor for high performance applications, high code density, and small program code size.

Keywords

digital signal processing chips; instruction sets; multimedia communication; parallel architectures; LILY processor; Tsinghua University; VLIW DSP processor; code density; multimedia applications; parallel instruction execution; program code size; very long instruction word; Assembly; Computer architecture; Digital signal processing; Hardware; Helium; Microelectronics; Parallel processing; Registers; Sun; VLIW; DSP (digital signal processor); VLIW (very long instruction word); assembler;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351602

Filename

5351602