DReNoC: A dynamically reconfigurable computing system based on network-on-chip

Author

Chen, Ying-Chun ; Du, Gao-Ming ; Geng, Luo-Feng ; Zhang, Duo-li ; Gao, Ming-Lun

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

71

Lastpage

74

Abstract

A dynamically reconfigurable computing system based on network-on-chip (DReNoC) is proposed, which consists of computing nodes and communication nodes. The computing node is a complete coarse-grained dynamically reconfigurable SoC named DReSoC. And the DReSoCs communicate with each other through on chip network routers. The proposed DReNoC has been implemented on the ALTERA STRATIX II EP2S180 DSP development board with 48063 Combinational ALUTs and 26211 logic registers. Experimental result of 8?8 matrix sequential matrix multiplications showed that, compared with a single-core system-on-chip (SoC) based on the standard Nios II processor, the speed-up ratio can reach 124.91.

Keywords

integrated circuit interconnections; network-on-chip; reconfigurable architectures; DReNoC; communication nodes; computing nodes; dynamically reconfigurable computing system; network-on-chip; on chip network routers; Circuit synthesis; Computer architecture; Computer networks; Concurrent computing; Energy consumption; High performance computing; Network-on-a-chip; Parallel processing; Streaming media; Sun; DReNoC; DReSoC; network-on-chip; reconfigurable computing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351605

Filename

5351605