DocumentCode :
2655511
Title :
Design of a high reliable L1 data cache with redundant cache
Author :
Li, Zhaolin ; Zhang, Xinyue ; Luo, Huiqing
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
41
Lastpage :
45
Abstract :
Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. To deal with multiple soft errors with little impact on hardware overhead and performance, this paper proposes a new cache memory system, in which redundant cache blocks are integrated into a set-associative L1 data cache. Each redundant cache block is used to store the replica of each ¿dirty¿data in correspondence with L1 data cache blocks. In order to realize the detection of multiple soft errors with little hardware overhead, a bit interleaving group parity code is adopted to detect multiple soft errors in L1 data cache blocks. Moreover, in order to increase the mapping rate between L1 data cache blocks and the redundant cache blocks, an early write-back based protocol is introduced, in which all dirty cache blocks are written back to L2 cache at the intervals of a determined cycle number. The proposed cache system can provide more powerful soft error protection than conventional error correction codes. Experiment results show that the cache system proposed in this paper can provide replicas for almost 100% of dirty cache blocks in L1 data cache on average.
Keywords :
cache storage; content-addressable storage; redundancy; IC technology improvement; bit interleaving group parity code; cache memory system; dirty cache block; hardware overhead; hardware performance; high-performance processor; memory latency; redundant cache block; set-associative L1 data cache; soft error detection; write-back based protocol; Cache memory; Computer errors; Delay; Error correction codes; Hardware; Information science; Interleaved codes; Laboratories; Protection; Protocols; L1 data cache; Multiple soft errors; Redundant cache; Reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351610
Filename :
5351610
Link To Document :
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